Translation Table Base Register - Texas Instruments OMAP5910 Technical Reference Manual

MPU Memory Management Unit
2.7.6.1 Translation Table Base
Figure 2–11.Translation Table Base Register
31
15 14 13
Translation
Table Base
2-30
The translation process is initiated when the on-chip TLB does not contain an
entry corresponding to the requested virtual address (that is, when a TLB-miss
occurs). The CP15 translation table base (TTB) register points to the base of
a table in physical memory, which contains section and page table descriptors.
The 14 LSBs of the TTB register are always set to zero, so the table must start
on a 16K-byte boundary.
Translation Table Base (TTB)
The translation table has up to 4096 32-bit entries, each describing 1M byte
of virtual memory. This allows the addressing of up to 4G bytes of virtual
memory.
16
0