Interrupt Level Registers (Ilr0; Interrupt Set Register (Isr) - Texas Instruments OMAP5910 Technical Reference Manual

Table 6–21. Binary-Coded Source FIQ Register (SIR_FIQ_CODE)
Bit Name
4–0 FIQ_NUM
Table 6–22. Control Register (CONTROL_REG)
Bit Name
1 NEW_FIQ_REG
0 NEW_IRQ_REG
Table 6–23. Interrupt Level Registers (ILR0...ILR31)
Bit Name
6–2 PRIORITY
1 SENS_EDGE
†
0 FIQ
† IRQ is the only valid setting fo this bit when used with the level 2 handler—it cannot be used to generate FIQ sources.
Table 6–24. Interrupt Set Register (ISR)
Bit Name
31–0 SWI[31:0]
Description
This register indicates the IRQ interrupt that is currently being
serviced by the MPU. Reading this register clears the
corresponding bit in the ITR register if the interrupt is configured
as edge triggered.
This register is only used by the level 1 handler, because the level 2 handler
cannot be programmed to generate FIQ interrupts.
Description
New FIQ agreement. Writing a 1 resets FIQ output, clears source
FIQ register, and enables new IRQ generation.
New IRQ agreement. Writing a 1 resets IRQ output, clears source
IRQ register, and enables new IRQ generation.
Value Description
Defines the priority level when the corresponding
interrupt is routed to IRQ or FIQ (31 down to 0)
0 Interrupt is falling-edge-triggered.
1 Interrupt is low-level-triggered.
0 Interrupt is routed to IRQ.
1 Interrupt is routed to FIQ.
Description
Software interrupt set register. Writing a 1 to any bit generates an
interrupt to the MPU if the corresponding ILRn is configured as
edge-triggered; otherwise no interrupt is generated. A read to this
register always returns 0x00000000.
Interrupt Handler Level 1 and Level 2 Registers
MPU Private Peripherals
Reset
Value
0
Reset
Value
0
0
Reset
Value
0
0
0
Reset
Value
0
6-23