Master Transmitter Mode, Rm = 1 - Texas Instruments OMAP5910 Technical Reference Manual

Figure 7–32. Master Transmitter Mode, RM = 1
Bus active
Start
Read I 2 C_STAT.
Is
No bus free
(BB=0)
?
Yes
Write I 2 C_CON
1
With 8605h.
n = 0 (data byte counter):
m = Number of data bytes
to be transferred
Read I 2 C_STAT.
Is
Yes
ACK returned
(NACK=0)
?
No
STT and STP are
cleared to 0 by hardware.
Reprogram
the registers.
STT = 1
No
(new start)
?
Yes
Start
Start is
address
generated.
is sent.
Is
send data
being requested
(XUDF=1)
?
Yes
Are
m bytes
Yes
transferred
(n. = m)
2
?
n = n + 2
Write I 2 C_DATA.
Read I 2 C_STAT.
Can
update
the registers
(XUDF=1)
?
No
STP = 1
?
End
3
New
START is
generated.
STOP is
generated.
DATA is
sent.
Inter-Integrated Circuit Controller
No
No
No
Yes
1
Set appropriate values to every
bit of I 2 C_CON. I 2 C_EN bit must be set
to 1 to take I 2 C out of reset condition. Setting
I 2 C_EN and setting other mode bits can be done
simultaneously.
2 Because RM=1. hardware counter does not run.
Thus, software counter counts the number of the
required transfer.
The I 2 C goes into slave receiver mode.
3
[EXPECTED COMMAND]
At the beginning,
(STT,STP) = (1.0)
in the middle,
(STT, STP) = (0.0)
At the end,
(STT, STP) = (0.1)
[EXPECTED I 2 C_IE]
I 2 C_IE = 00000b
MPU Public Peripherals 7-89