Accessing The Translation Table Level 1 Descriptors - Texas Instruments OMAP5910 Technical Reference Manual

2.7.6.2 Level 1 Fetch
Figure 2–12. Accessing the Translation Table Level 1 Descriptors
31
31
31
31
Bits 31–14 of the TTB register are concatenated with bits 31–20 of the virtual
address to produce a 30-bit address (see Figure 2–12) by accessing the
translation table level 1 descriptors (see Section 2.7.6.3). This address selects
a four-byte translation table entry, which is a level 1 descriptor for either a
section or a page table.
20 19
Table index
Translation base
18
Translation base
Virtual Address
Section index
Translation table base
14 13
14 13
First-level descriptor
MPU Memory Management Unit
12
2 1
Table index
MPU Subsystem
0
0
0
0
0
0
2-31