Data Cache Configuration - Texas Instruments OMAP5910 Technical Reference Manual

Data Cache
2.4 Data Cache
2.4.1 D-Cache Operation
Table 2–1. Data Cache Configuration
C_CP15 C_MMU
0 X
1 0
Note: The load multiple instruction does not perform a burst read.
2-6
The 8K-byte data cache (D-cache) has 512 lines of 16 bytes arranged as a
two-way set-associative cache. It uses the virtual addresses generated by the
processor. The D-cache is always reloaded one line at a time, because it
always requires the MMU to be enabled. The MMU can operate in write-
through (WT) or in copy-back (CB) mode. The translation lookaside buffer
(TLB) descriptors that are placed in memory determine which mode is used.
You can enable or disable the D-cache via the CP15 control register: the
D-cache is disabled and flushed upon reset. The D-cache supports byte,
half-word, and word accesses.
The D-cache is always disabled when the MMU is off.
If the D-cache is enabled (C_CP15 = 1), it is searched whenever the processor
performs a data load or store. If the cache hits on a load, data is returned to
the core regardless of the C_MMU bit. If a cache read misses, the C_MMU bit
is examined. If it is 1, a line fetch is performed and the line is written to the cache
following an LRU (least recently used) replacement algorithm. If C_MMU is 0,
a single external access is performed and the cache is not updated. Stores that
hit the D-cache always update it, regardless of the C_MMU bit, to keep the
D-cache contents consistent with the external memory. Stores that miss do not
update the D-cache (see Table 2–1).
B_MMU Functional Description
X No cache search
X Cache search active
• Read and write misses are not cached.
• Cache serves read hits.
• Write hits update the cache.
• Read misses and writes generate external accesses.