Address Translation Process - Texas Instruments OMAP5910 Technical Reference Manual

2.7.6 Translation Process
Figure 2–10. Address Translation Process
Section
transistor
fault
Section
No access (D0)
domain
Reserved (10)
fault
Section
permission Violation
fault
The MMU translates virtual addresses generated by the CPU into physical
addresses to access the external memory and checks the access permission
using a translation look-aside buffer (TLB) (see Figure 2–10).
The MMU table walking hardware is used to add entries to the TLB.
Check address alignment
Get level 1 descriptor
Invalid
Section
Check domain status
Section
Client (0.1)
Check access
permissions
Virtual address
Page
Get page
table entry
Page
Client (0.1)
Manager (0.1)
Check access
permissions
Physical address
MPU Memory Management Unit
Alignment
Misaligned
fault
Page
translation
Invalid
fault
Page
No access (D0)
domain
Reserved (10)
fault
Subpage
Violation permission
fault
MPU Subsystem 2-29