Read Timing Diagram; Reset Timing Diagram; Write Timing Diagram - Texas Instruments OMAP5910 Technical Reference Manual

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Timing Diagrams

Figure 7–65. Read Timing Diagram

Must be driven low by host for DS,

driven low by slave on HDQ

Figure 7–66. Reset Timing Diagram

Sent by host

Figure 7–67. Write Timing Diagram

Figure 7–65 through Figure 7–67 show the timing diagram for the read, reset,

and write. In HDQ, the reset pulse only contains the initialization and not the

presence pulse. The timing required for the various signals are specified in the

The master works at the timing of the HDQ interface, which encompasses the

HDQ and the 1-Wire timing. Therefore, in 1-Wire mode, the master runs slower

than the full performance capability of the protocol.

Sent by host

HDQ and 1-Wire Protocols

MPU Public Peripherals