Emiff Priority Handler; External Memory Interface Fast Signal List Nil - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
Table 7.

External Memory Interface Fast Signal List NIL

3.3.1

EMIFF Priority Handler

34 Memory Interface Traffic Controller
Signal Name
SDRAM.A[12:0]
SDRAM.D[15:0]
SDRAM.CLK
SDRAM.BA[1:0]
SDRAM.CKE
SDRAM.RAS
SDRAM.CAS
SDRAM.WE
SDRAM.DQML
SDRAM.DQMU
This memory interface has two software-selectable priority algorithms for
resolving simultaneous access requests: least recently used and dynamic
priority. The priority scheme is shared with the EMIFS and IMIF and it is set in
the OMAP5910 configuration
FUNC_MUX_CTRL_0). See SPRU671, MPU Subsystem Reference Guide,
for details on configuration registers.
Least recently used
-
A round-robin arbitration scheme. The highest priority requestor is the
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one that least recently accessed the memory.
Dynamic priority
-
Dynamic priority uses high- and low-priority queues.
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Each requestor, except the MPU, has a time-out register allocated to it
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(see Time-Out Registers in Section 4). These registers hold the
number of clock cycles that a low-priority queue request has to wait
before it is moved from the low-priority queue to the high-priority
queue.
At reset, all requestors are initially in the low-priority queue and the
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time-out registers are set to minimum value for each requestor. You
must program these registers before using dynamic priority.
I/O Description
O SDRAM address bus
I/O Data from SDRAM
O Clock to SDRAM
O SDRAM bank select
O SDRAM clock enable
O SDRAM RAS
O SDRAM CAS
O SDRAM write enable
O Lower byte 3-state
O Upper byte 3-state
registers (bit 20, LRU_SEL
SPRU673
in