Features - Texas Instruments OMAP5910 Technical Reference Manual

Features

1.3 Features
1-6
The OMAP5910 device has the following features:
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Ability to support reduced instruction set computer (RISC) and DSP
operating systems
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TI925T MPU subsystem with:
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Instruction cache (16K bytes) and data cache (8K bytes)
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Memory management unit (MMU)
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A 17-word write buffer (WB)
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DSP subsystem (C55x DSP core and subsystems) with:
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Internal 32K-word dual-access RAM (DARAM), 48K-word single
access RAM (SARAM), 16K-word ROM
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Software-configurable instruction cache (12K words, 128-bit line size,
2-way set-associative + RAM set)
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Hardware accelerators for video processing, pixel interpolation, and
motion estimation
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Six-channel DMA controller for high-speed data movement without
DSP intervention
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DSP MMU for address translation and access permission checks
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System DMA controller with:
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Six ports and nine independently programmable generic channels
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An additional dedicated DMA channel tied to the liquid crystal display
(LCD) controller
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Ability to transfer 8-,16-, or 32-bit data between the external memory,
the MPU, and peripherals with byte alignment and packing capability
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Ability to perform simultaneous transfers (single or multiple burst) if no
resources conflict
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Low-power design (no clocking when idle)
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Two external memory interfaces that allow glueless hookup to:
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A 16-bit bus interface to external memory interface slow (EMIFS),
such as flash/SRAM/ROM/page-mode ROM/SB flash/DPRAM), with
128M bytes of memory space
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A 16-bit bus interface to external memory interface fast (EMIFF), such
as memory SDRAM, with 64M bytes of memory space