Sdram Clock Disable; Endian Conversion Control; Sdram Access Timing Diagrams - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
3.3.6

SDRAM Clock Disable

3.3.7

Endian Conversion Control

3.3.8

SDRAM Access Timing Diagrams

38 Memory Interface Traffic Controller
beyond 64 milliseconds, and the SDRAM controller does not autorefresh
during reset, data is corrupted. Setting the RFRSH_RST bit in the EMIF fast
interface SDRAM configuration register 2 (EMIFF_SDRAM_CONFIG_2)
avoids SDRAM data corruption for this case by automatically placing the
SDRAM in self-refresh mode prior to warm reset being applied to the traffic
controller. The SDRAM controller continues in self-refresh mode until the reset
is unasserted. Note that RFRSH_RST applies only in the case of warm reset.
For cold reset, SDRAM is not set to self-refresh regardless of the state of
RFRSH_RST.
Caution: Self-Refresh Mode
When the EMIFF SDRAM is in self-refresh mode, the EMIFF does
not respond to TIPB requests including MRS writes. To respond,
the SLRF bit must be cleared by firmware. Writes to TC registers
which would normally cause EMIFF to perform an action have no
effect while EMIFF is in self-refresh mode. If an MRS write is
attempted while EMIFF is in self-refresh mode, there is a pending
MRS request. This prevents the traffic controller from idling and
therefore prevents the device from entering deep sleep mode. The
MRS request is not serviced until the SLRF bit is cleared.
The EMIF fast SDRAM clock signal (SDRAM.CLK) is disabled using these
steps:
1) Set the PDE bit field of the EMIF slow interface configuration register.
2) Set one (or both) of the following bit fields in the EMIF fast SDRAM
configuration register 1
a) Set the SLRF to place the SDRAM into self-refresh mode
b) Set the PWD to place the SDRAM into power-down mode
3) Set the CLK bit field of the EMIF fast interface SDRAM configuration
register 1 to stop the clock
The traffic controller registers include a register to control endian
conversion in the DSP memory management unit. For details, see Table 26,
Endianism Register (ENDIANISM).
Figure 8 through Figure 18 show the SDRAM timing diagrams. Burst
accesses shown here might not be achievable by all initiators of EMIFF
transactions. See Section 3.3.2 for more detail on bursting behavior.
SPRU673