Dma Controller Ports; Updating Addresses In A Channel - Texas Instruments OMAP5910 Reference Manual

Multimedia processor dsp subsystem
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7.2.9

Updating Addresses in a Channel

7.2.10
Data Packing Capability
Table 47. DMA Controller Ports
SPRU890A
During data transfers in a DMA channel, the DMA controller begins its read and
write accesses at the start addresses you specify (see section 7.2.8). In many
cases, these addresses must be updated so that data is read and written at
consecutive or indexed locations after a data transfer has begun. You can
configure address updates at two levels:
Block-level
address
-
(AUTOINIT = 1 in DMACCR), block transfers can occur one after another
until you turn off auto-initialization or disable the channel. If you want
different start addresses for the block transfers, you can update the start
addresses between the block transfers.
Element-level address updates. You can have the DMA controller update
-
the source address and/or the destination address after each element
transfer. At the end of an element transfer, the source address held by the
DMA controller is the address of the last byte that was read from the
source. Likewise, after a transfer, the destination address held by the DMA
controller is the address of the last byte that was modified at the
destination. Through software control, you can make sure the source
address points to the start of the next element, and you can make sure the
element will be precisely positioned at the destination. Choose an
addressing mode for the source with the SRCAMODE bits in DMACCR.
Choose an addressing mode for the destination with the DSTAMODE bits
in DMACCR. If you choose a single-index or double-index addressing
mode, you must load the appropriate index register or registers (see
section 7.3.11).
The five DMA controller ports have various widths and support various sizes
of data accesses.
DMA Port
SARAM
DARAM
EMIF
Peripheral
MPUI
updates.
In
the
Port Width
Access Sizes Supported (bytes)
32
32
32
16
16
DSP DMA
auto-initialization
mode
2, 4
2, 4
1, 2, 4
2, 4
2
DSP Subsystem
139

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