(Emifs_Cs0_Config; Memory Type - Texas Instruments OMAP5910 Technical Reference Manual

Traffic Controller Memory Interface Registers
Table 4–13. EMIF Slow Chip-Select Configuration Registers
(EMIFS_CS0_CONFIG...EMIFS_CS3_CONFIG) (Continued)
Bit Field
7:4 RDWST
3 Reserved
2 RT
1:0 FCLKDIV
Table 4–14. Memory Type
4-46
Value Description
Number of wait states for asynchronous read
operation (see Table 4–15). Number of inserted
clock cycles in protocol (value matches the value
programmed in Intel flash devices).
Read is undefined. Writes must be zero.
Retiming control register:
0 The data is not retimed.
1 The data coming from the external bus is retimed
with the CLK.
EMIFS internal reference clock divider:
00 Reference clock = TC clock divided by 1
01 Reference clock = TC clock divided by 2
10 Reference clock = TC clock divided by 4
11 Reference clock = TC clock divided by 6
RDMODE
000 Asynchronous read
001 Page mode ROM read—4 words per page
010 Page mode ROM read—8 words per page
011 Page mode ROM read—16 words per page
100 Synchronous burst read
Others Reserved. Do not use.
Access
R/W
R/W
R/W
R/W
Memory
Reset
Value
1111
U
0
11