External Aborts - Texas Instruments OMAP5910 Technical Reference Manual

MPU Memory Management Unit

2.7.12 External Aborts

2.7.13 Buffered Writes
2-46
-
Section: If the level 1 descriptor defines a section-mapped access, its AP
bits define whether or not the the access is allowed (see Table 2–24).
Their interpretation is dependent upon the setting of the S bit (CP15 con-
trol register bit 8). If the access is not allowed, a section permission fault
is generated.
-
Subpage: If the level 1 descriptor defines a page-mapped access, the
level 2 descriptor specifies four access permission fields (ap3..ap0), each
corresponding to one quarter of the page. ap0 corresponds to the subpage
located at the lowest addresses. The selected AP bits are then interpreted
in the same way as for a section and may generate a subpage permission
fault.
In addition to the MMU-generated aborts, the TI925T has an external s_abort
port, which can be used to flag errors on external memory accesses. However,
not all accesses can be aborted this way, so this signal must be used with great
care. This section describes the restrictions.
The accesses listed below can be aborted and restarted safely. In the case of
an interlocked read-write (SWAP instruction) in which the read aborts, the
write does not happen.
-
Reads
-
Unbuffered writes
-
Level-1 descriptor fetch
-
Level-2 descriptor fetch
-
Interlocked read-write (SWAP)
-
Cacheable reads (line fetches)
A cache line fetch can be safely aborted on any word in the transfer. If an abort
occurs during the line fetch, the cache line is invalidated. In addition, if the abort
happens upon or before the instruction the TI925T requested, the instruction
is aborted. If the abort happens after, the cache line is simply marked as
invalid.
Buffered writes cannot be aborted externally. Therefore, the system must be
configured in such a way that it does not perform buffered writes to areas of
memory that can generate an external abort.
There are three instances of MMU: the DSP MMU, the MPU instruction cache
MMU, and the MPU data cache
Because there are multiple MMUs, it is the responsibility of the OS (system
software) to ensure data coherence.
MMU. The MPU MMU is that of the TI925T.