Synchronous Burst Read With Page Alignment - Texas Instruments OMAP5910 Reference Manual

Figure 6.

Synchronous Burst Read With Page Alignment

TC clock
FLASH.CLK
(FCLKDIV=1)
FLASH.CLK
(FCLKDIV=2)
FLASH.CLK
(FCLKDIV=4)
FLASH.CLK
(FCLKDIV=6)
FLASH.CS_[X]
FLASH.D
FLASH.CLK
FLASH.A
FLASH.CS_[X]
FLASH.ADV
FLASH.BAA
FLASH.RDY
FLASH.OE
FLASH.D
SPRU673
Synchronous burst read operation (1/2)
1 TC clock cycles
(RDWST+1)xFCLKDIV TC clock cycles
2 TC clock cycles
(RDWST+1)xFCLKDIV TC clock cycles
4 TC clock cycles
6 TC clock cycles
Synchronous burst read operation (2/2)
Address valid
Defined by first
access latency in
Flash configuration
register
Data strobing edges
(RDWST+1)xFCLKDIV TC clock cycles
(ROWST+1)
x
FCLKDIV TC
clock cycles
Memory Interface Traffic Controller
Memory Interfaces
First data
valid on this edge
31