Cp15 Register Summary; Reading From Cp15 Register 0; Field - Texas Instruments OMAP5910 Technical Reference Manual

Table 2–3. CP15 Register Summary
Register Reads
0 ID register
1 Control register
2 Translation table base
3 Domain access control
4 Unpredictable
5 Fault status
6 Fault address
7 Unpredictable
8 Unpredictable
9 Unpredictable
10 TLB lock-down
11 Unpredictable
12 Unpredictable
13 PID
14 Unpredictable
15 TI operations
2.6.2.1 ID Register and Cache Information Register
-
Ignored: Writing to such a location does not affect the system behavior.
-
VA: Virtual address (data or instruction)
In all cases, reading data values from or writing any data values to any CP15
register, including those fields specified as unpredictable or SBZ, causes no
permanent damage to the TI925T.
Writes
Ignored
Control register
Translation table base
Domain access control
Ignored
Fault status
Fault address
Cache operations
TLB operations
Ignored
TLB lock-down
Ignored
Ignored
PID
Ignored
TI operations
Reading from CP15 register 0 returns either an identification defined by archi-
tecture and implementation for the processor or information on the cache,
depending on the op-code_2 used. CRm SBZ when reading.
Writing to register 0 is ignored.
Coprocessor 15
Access RD
Read-only 31..0
Read/Modify/Write 14..0
Read/Write 31..14
Read/Write 31..0
-
Read/Write 8..0
Read/Write 31..0
Write-only 31..0
Write-only 31..0
-
Read/Write 31..0
-
-
Read/Write 31..25
-
Read/Write 31..0
MPU Subsystem 2-11