Dsp Endian Conversion, 32-Bit Aligned Data - Texas Instruments OMAP5910 Technical Reference Manual

Figure 2–24. DSP Endian Conversion, 32-Bit Aligned Data
EMIF
data out
DSP
(big endian)
EMIF
data in
EMIF
address
Controls
Controls
Packing and
unpacking
Controls
controls
Note: The steering logic puts the byte/word/double-word in appropriate formats.
Figure 2–24 shows the endian conversion at the DSP MMU interface bounda-
ry. The byte and word swapping is done by decoding the data width and data
size, then repacking the data into the appropriate formats.
The byte-steering logic provides a mechanism to convert from big to little, little
to big, or upper and lower word swap for program code and data accesses.
DSP write swapping buffers
Byte 3
Bytes
Byte 2
steering
logic
Byte 1
(write)
Byte 0
(Little endian )
DSP read swapping buffers
Byte 0
Bytes
Byte 1
Steering
Logic
Byte 2
(Read)
Byte 3
(Big endian)
DSP endian conversion for 32-bit aligned data
D_in
Traffic
controller
Async
DSP
(little
FIFO
MMU
endian)
(Little
(Little
endian
endian
D_out
MPU Subsystem
Endianism Conversion
Flash
(little
endian)
SDRAM
(little
endian)
Internal
SRAM
(little
endian)
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