Imif Operation; External Memory Interface Slow; External Memory Interface Slow Signal List - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
3.1.2

IMIF Operation

3.2

External Memory Interface Slow

Table 4.

External Memory Interface Slow Signal List

Signal Name
FLASH.RDY
FLASH.WP
FLASH.CLK
FLASH.RP
FLASH.CS0
FLASH.CS1
†
FLASH.CS2
FLASH.CS3
†
FLASH.BAA
FLASH.OE
FLASH.WE
FLASH.ADV
FLASH.D[15:0]
†
FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu-
ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default.
22 Memory Interface Traffic Controller
The 192K bytes of internal SRAM are selected by an internal chip select based
on the appropriate address decode. The interface to the SRAM is 32 bits wide
and provides support for single and burst accesses. The SRAM operates at
the frequency of the traffic controller.
The EMIFS interfaces traditional and synchronous flash, asynchronous
SRAM, and ROM. The interface can drive up to four devices with one of four
chip-select pins. Each chip-select pin has a corresponding register to specify
the protocol for the associated external device.
Table 4 shows the EMIFS signal list.
I/O Bus Description
I − Ready/busy signal from device
O − Write protection
O − Clock signal for flash device
O − Flash power-down/reset
O − Active-low chip-select for device
O − Active-low chip-select for device
O − Active-low chip-select for device
O − Active-low chip-select for device
O − Active-low burst advance acknowledge for Advanced Micro Devices
(AMD) burst flash
O − Active-low output enable
O − Active-low write enable
O − Active-low address valid
I/O 15 −0 Flash data bus from external device
SPRU673