Registers - Texas Instruments OMAP5910 Technical Reference Manual

Registers

5.6 Registers
Table 5–10. DMA Controller Registers
Name
DMA_GCR
DMA_CSDP_CH0
DMA_CCR_CH0
DMA_CICR_CH0
DMA_CSR_CH0
DMA_CSSA_L_CH0
DMA_CSSA_U_CH0
DMA_CDSA_L_CH0
DMA_CDSA_U_CH0
DMA_CEN_CH0
DMA_CFN_CH0
DMA_CFI_CH0
DMA_CEI_CH0
DMA_CPC_CH0
DMA_CSDP_CH1
5-34
Table 5–10 describes the DMA controller registers.
Note:
The DMA control registers are part of a register superset for multiple OMAP-
based devices. They are defined for a 16-port, 16-channel DMA controller.
Thus as generic as possible a register mapping is provided, so some regis-
ters may appear to be almost empty. Only the 16 LSBs are used; in fact, the
DMA registers must always be accessed as 16-bit registers.
Base address for system DMA: FFFE–D800
Description
Global control
Channel 0 source destination
parameters
Channel 0 control
Channel 0 interrupt control
Channel 0 status
Channel 0 source start
address—lower bits
Channel 0 source start
address—upper bits
Channel 0 destination start
address—lower bits
Channel 0 destination start
address—upper bits
Channel 0 element number
Channel 0 frame number
Channel 0 frame index
Channel 0 element index
Channel 0 channel progress counter
Channel 1 source destination
parameters
Size
R/W Address
(Bits)
R/W 16 0xFFFEDC00
R/W 16 0xFFFED800
R/W 16 0xFFFED802
R/W 16 0xFFFED804
R 16 0xFFFED806
R/W 16 0xFFFED808
R/W 16 0xFFFED80A
R/W 16 0xFFFED80C
R/W 16 0xFFFED80E
R/W 16 0xFFFED810
R/W 16 0xFFFED812
R/W 16 0xFFFED814
R/W 16 0xFFFED816
R/W 16 0xFFFED818
R/W 16 0xFFFED840
Reset Value
0x0008
0x0000
0x0000
0x0003
0x0000
U
U
U
U
U
U
U
U
U
0x0000 0000