Timer Interrupt Period - Texas Instruments OMAP5910 Technical Reference Manual

7.5.1.1 Overriding Normal Counting
7.5.1.2 Loading/Autorestart of the Timer
7.5.1.3

Timer Interrupt Period

Table 7–35. Timer Interrupt Period
Normal operation can be overridden by using two bits in the timer control
register (TCR):
-
The timer reload bit (TRB) causes the counter to be reloaded on the next
clk32-kHz cycle (whether or not the timer is counting).
-
The timer start stop bit (TSS) causes the counter to be stopped on the next
clk32-kHz cycle. When the timer is stopped, the content of the counter is
frozen.
Loading the counter in the timer can be done in two fashions:
-
Write a 1 to the TRB bit in the timer control register (TCR).
-
Wait until the counter reaches zero and is reloaded from its register if the
autorestart bit (ARL) in the timer control register (TCR) is set to 1. If not,
then the timer is stopped.
The timer interrupt period is defined by the value loaded into the tick value
register (TVR).
The timer interrupt rate is as follows:
IRQ rate =(TVR+1) / 32768
TVR Value
0x000000
0x00028F
0xFFFFFF (Value at reset)
32-kHz Timer
Interrupt Period
30.5 µs
19.9 ms
512 s (8 min 32 s)
MPU Public Peripherals 7-47