Calculating The Descriptor Address In A Coarse - Texas Instruments OMAP5910 Reference Manual

6.2.6.5 Coarse Page Tables
Figure 44. Calculating the Descriptor Address in a Coarse Page Table
31
Course page table base address
31
Page table base address
Legend: AP = Access Permissions: 00 or 01 = no access, 10 = read only, 11 = full access; X = don't care
SPRU890A
Coarse page tables can be used to map large and small pages of virtual
memory to physical memory. Each coarse table must contain 256 entries.
Follow these rules when using coarse page tables:
The start address of a coarse page table must be aligned on a 1024-byte
-
boundary; that is, the last 10 bits of its start address must be zeros.
A descriptor for a large page must be repeated sixteen times. The
-
repeated descriptor must start at an entry number that is a multiple of
sixteen. As described in section 6.2.2, only one entry is required in the TLB
to translate a large page.
Descriptors for tiny pages cannot be used.
-
The address of the second-level descriptor is determined by using the course
page table base address (contained in the first-level descriptor) and a
second-level table index. The second-level table index is taken from the DSP
virtual address.
Figure 44 describes how to generate the descriptor address for coarse page
tables.
23 20 19
X 2nd level table index
Notice that the MMU indexes the coarse table as if the entries were specifying
small pages. That is, it always selects 1 of 256 entries. However, the MMU
uses 16 bits from the second-level descriptor as a base address for a large
page and 20 bits for a small page (see Figure 41 and Figure 42, respectively).
This behavior means that when large pages are used, the descriptor for a large
page must be repeated sixteen times in the coarse page table.
DSP Memory Management Unit
First-level descriptor contents
10 9
X
DSP virtual address
12 11
Second-level descriptor address
10 9
2nd level table index
DSP Subsystem
0
2 1
0 1
0
X
2 1 0
0 0
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