Mmc System Status Register (Mmc_Stat) - Texas Instruments OMAP5910 Technical Reference Manual

Table 7–100. MMC System Status Register (MMC_STAT)
Bit Name
15 Reserved
14 Card_Err
13 Card_IRQ
12 OCR_busy
11 A_Empty
10 A_Full
9 Reserved
8 Cmd_CRC
7 Cmd_timeout
6 Data_CRC
5 Data_timeout
4 EOF_Busy
3 Block_RS
2 Card_Busy
1 Reserved
0 End_of_Cmd
Card Status Error (Card_Err)
Description
Card status error in response
Card IRQ received (following CMD40)
OCR busy (following CMD1 or ACMD41)
Buffer almost empty
Buffer almost full
Command CRC error
Command response time-out (no response)
Data CRC error
Data response time-out (no response)
Card exit busy state
Block received/sent
Card enter busy state
End of command phase
Common to all bits:
-
The local host can only clear a set bit location by writing a 1 into the bit
location. A write 0 has no effect.
-
When a bit location is set to 1 by the core, an interrupt is signaled to the
local host if the interrupt was enabled.
MMC/SD mode only.
The core automatically sets this bit (14) when there is at least one error in a
response of type R1, R1b or R6. Only bits referenced as type E (error) can set
a card status error (see Table 7–101).
MMC/SD Host Controller
MPU Public Peripherals 7-135