Dsp Memory Space - Texas Instruments OMAP5910 Technical Reference Manual

Figure 3–6. DSP Memory Space
Byte address
00_0000
MMRs
00_0100
DARAM
64K bytes–0X100 bytes
8 blocks
(Table A)
01_0000
SARAM
96K bytes
12 blocks
02_8000
External to
DSP subsystem
16 MB
mapped by
DSP MMU
into MPU 32-bit
address space
FF_8000
PDROM
32K-byte
masked ROM
Reset vectors
FF_FF00
NMI vectors
Emu/test vectors
L2 peripherals
TC abort
Bus error
FF_FFFE
Note: Byte addresses 0xFF8000-0xFFFFFF map to PDROM for mpnmc = 0; otherwise, this range is mapped externally
Word address
00_0000
00_0080
00_8000
00000
00800
01000
01_4000
01800
02000
02800
03000
03800
04000
04800
05000
05800
06000
06800
07000
07800
08000
08800
09000
09800
0A000
7F_C000
0A800
0B000
0B800
0C000
0C800
0D000
0D800
0E000
0E800
7F_FF80
0F000
0F800
32 interrupt
daram0
vectors
daram1
daram2
daram3
daram4
daram5
7F_FFFF
daram6
daram7
The TMS320C55x DSP has 24-bit unified address space for both data and
program references.
* Program accesses are specified and displayed as byte addresses.
* Data objects are word addressable and are specified by 16-bit
word addresses.
* The DMA controller references byte addresses.
To access control and data registers associated with various OMAP5910
peripherals, the DSP uses 16-bit I/O space. This space is referenced
by using appropriate I/O access qualifiers with load or store instructions.
Restrictions apply for data objects spanning 64K-word (128K-byte) boundaries.
See TMS320C55x DSP CPU Reference Guide (SPRU371).
I/O Space
Byte Word
TIPB bridge 00000
00400
00800
EMIF
DMA 00C00
01000
I-Cache 01400
01800
00C00
02000
02400
Timer1 02800
Timer2 02C00
Timer3 03000
WD_Timer 03400
03800
03C00
CLKM2 04000
04400
L2 Int handler 04800
04C00
05000
05400
05800
05C00
06000
06400
06800
06C00
07000
07400
07800
07C00
Table A DARAM block boundaries
Byte address Word address
00 _0000 00 _0000
00 _2000 00_1000
00 _4000 00_2000
00 _6000 00_3000
00 _8000 00_4000
00 _A000 00_5000
00 _C000 00_6000
WORD Addr
00 _E000 00_7000
DSP Memory
Byte Word
10000 UART1
10800 UART2
11000
McBSP1
11800 08C00
MCSI2
12000
12800 MCSI1
13000
13800 09C00
I-Cache
14000 0A000
14800 0A400
15000 0A800
15800 0AC00
16000 0B000
16800 0B400
McBSP3
17000 0B800
17800 0BC00
18000 0C000
18800 0C400
19000 0C800
19800 UART3 0CC00
1A000 0D000
1A800 0D400
1B000 0D800
1B800 0DC00
1C000 0E000
1C800 0E400
UART1,2,3 shading SW
1D000 0E800
1D800 0EC00
1E000 GPIO 0F000
1E800 0F400
1F000 Mailbox 0F800
1F800 DSP MPUI register 0FC00
Table B SARAM block boundaries
Byte address Word address
saram0 01 _0000 00_8000
saram1 01 _2000 00_9000
saram2 01 _4000 00_A000
saram3 01 _6000 00_B000
WORD Addr
saram4 01 _8000 00_C000
saram5 01 _A000 00_D000
saram6 01 _C000 00_E000
saram7 01 _E000 00_F000
saram8 02 _0000 01_0000
saram9 02 _2000 01_1000
saram10 02 _4000 01_2000
saram11 02 _6000 01_3000
DSP Subsystem
08000
08400
08800
09000
09400
09800
.
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