Global Flush Register (Gflush_Reg) - Offset Address (Hex): 3C; Individual Flush Register (Flush_Entry_Reg) - Offset Address (Hex):40; Cam Entry Register Msb (Read_Cam_H_Reg) - Offset Address (Hex); Cam Entry Register Lsb (Cam_Cam_L_Reg) - Offset Address (Hex) - Texas Instruments OMAP5910 Technical Reference Manual

Table 2–42. Global Flush Register (GFLUSH_REG) – Offset Address (hex): 3C
Bit Function
15–1 Reserved
0 Toggle bit. Flush all nonprotected TLB entries when 1 is written.
Always 0 when read. Automatically reset.
Table 2–43. Individual Flush Register (FLUSH_ENTRY_REG) – Offset Address (hex):40
Bit Function
15–1 Reserved
0 Toggle bit. Active high. Always 0 when read.
Table 2–44. CAM Entry Register MSB (READ_CAM_H_REG) – Offset Address (hex): 44
Bit Function
15–10 Reserved
9–0 Table index level 1 MSB
Table 2–45. CAM Entry Register LSB (CAM_CAM_L_REG) – Offset Address (hex): 48
Bit Value Function
15–10 Table index level 1 LSB
9–4 Tiny page bits 9–0 (10 bits long)
Small page bits 9–2 (8 bits long)
Large page bits 9–6 (4 bits long)
DSP Memory Management Unit
Value at
Hardware
Reset
Size Access
15
1 R/W
Value at
Hardware
Size Access Reset
15
1 R/W
Value at
Hardware
Size Access Reset
6
10 R/W
Value at
Hardware
Reset
Size Access
6 R/W
6 R/W
MPU Subsystem
0
0
0
0
0
2-53