Sdram Single Half-Word Followed By A Read Burst 6 Half-Words - Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
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Memory Interfaces
Figure 14.

SDRAM Single Half-Word Followed by a Read Burst 6 Half-Words

ACTV0
WRITE
STOP
DEA
ACTV0
WRIT
STOP
C
E
ACCESS_REG
2
2
ACCESS_GRANT
t
= 9
rc
COMMAND
t
= 5
ras
ADDRESS
B0/R0
B0/C0
B0/R0
B0/R5
DQ
D
D
D
D
D
D
D
C0+1
C5+1 C5+2 C5+3 C5+4 C5+5
C5+6
CURRENT_COL
C0
C5
C5+1 C5+2 C5+3 C5+4
C5+5
CURRENT_SIZE
0
4
3
2
1
0
5
DVALID
SAVE_ADD
LAST_DATE
WRITE (burst reduced to 1) is followed by a WRITE (6) in the same bank but on a different page..
Note:
SPRU673
Memory Interface Traffic Controller
45

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