Emifs Dual-Port Ram Interface Mode; External Memory Interface Fast - Texas Instruments OMAP5910 Reference Manual

EMIFS CS Active Widths for Asynchronous Reads/Writes (Continued)
Table 6.
FCLK CS Active Width Read
DIV (TC Cycles)
/4 4 * (RDWST + 1) + 4
/6 6 * (RDWST + 1) + 6
3.2.9

EMIFS Dual-Port RAM Interface Mode

3.3

External Memory Interface Fast

SPRU673
The OMAP5910 EMIFS includes a programmable mode associated with the
FLASH.CS2 chip select pin to support external devices that require a valid
flash address before chip select is active. An example of such a device is a dual
port RAM (DPRAM). When DPRAM mode is enabled, the low transition of
FLASH.CS2 is delayed to ensure that address is valid. The low to high
transition of FLASH.CS2 is not changed regardless of the mode setting.
EMIFS DPRAM mode is programmed in the OMAP5910 configuration
registers using bit 22, CONF_MOD_DPRAM_ENABLE_R, in register
MOD_CONF_CTRL_0. See Chapter 6, MPU Private Peripherals, for details
on configuration registers.
DPRAM interface mode is only applicable to EMIFS chip-select FLASH.CS2.
Also note that the FLASH.CS2 pin multiplexes the FLASH.BAA function (see
Table 4), To activate the DPRAM interface mode, the user must first ensure
that OMAP5910 pin multiplexing has FLASH.CS2 selected, then program for
DPRAM interface configuration as described above. The FLASH.CS2 pin
asserts only once for 32-bit access, even though it is divided into two 16-bit
accesses.
The EMIFF can interface with synchronous DRAM (SDRAM). The interface
directs all the transactions to the SDRAM device. The bus width is 16 bits.
Table 7 shows the EMIFF signal list.
CS Active Width Write
(TC Cycles)
4 * (WRWST + WELEN + 1) + 8
6 * (WRWST + WELEN + 1) + 12
Memory Interface Traffic Controller
Memory Interfaces
33