Start And Stop Conditions - Texas Instruments OMAP5910 Technical Reference Manual

2
7.8.1.3 I C Bus Base Principal
Figure 7–24. Data Validity on the I
Figure 7–25. Start and Stop Conditions
The data on the SDA line must be stable during the high period of the clock.
The high and low states of the data line can only change when the clock signal
on the SCL line is low (see Figure 7–24).
2
C Bus
SDA
SCL
2
The I C module generates start and stop conditions when it is configured as
a master (see Figure 7–25):
-
Start condition is a high-to-low transition on the SDA line while SCL is high.
-
Stop condition is a low-to-high transition on the SDA line while SCL is high.
The bus is considered busy after the start condition (BB = 1) and free after the
stop condition (BB = 0).
SDA
SCL
Start
condition (S)
Data line Change
stable, of data
data valid allowed
MPU Public Peripherals
Inter-Integrated Circuit Controller
Stop
condition (P)
7-59