Sdram Read Single Half-Word Followed By A Write Byte - Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
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Figure 16.

SDRAM Read Single Half-Word Followed by a Write Byte

ACTV0
ACCESS_REG
2
ACCESS_GRANT
COMMAND
ADDRESS
B0/R0
DQ
DQMU
DQMx
DQML
CURRENT_COL
CURRENT_SIZE
DVALID
SAVE_ADD
LAST_DATE
READ (burst reduced to 1) is followed by a single-byte WRITE in the same bank but on a different page.
Note:
SPRU673
READ
DEA
C
2
t
= 4
ras
B0/C0
B0/R0
L = 3
Q
t
= 9
rc
C0+1
C0
0
ACTV0
WRIT
STOP
E
B0/R5
B0/C5
D
C5+1
C5
0
Memory Interface Traffic Controller
Memory Interfaces
47

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