Edge-Triggered/Level-Sensitive Control Register Low; Edge-Triggered/Level-Sensitive Control Register High - Texas Instruments OMAP5910 Technical Reference Manual

Table 8–31. Edge-Triggered/Level-Sensitive Control Register Low
Bit Name
15–0 CHx Trig/Level
Table 8–32. Edge-Triggered/Level-Sensitive Control Register High
Bit Name
15–8 Reserved
7 Host Interrupt
Trig/Level
6 NMI Trig/Level
5–0 CHx Trig/Level
Value Description
This bit defines whether channel CHx is edge- or level-
sensitive where CHx corresponds to interrupt channels
nXIRQ[15:0]. Channels nXIRQ[15:0] correspond to the
DSP level 1 interrupts IRQ17:2, respectively.
0 CHx is level-sensitive.
1 CHx is edge-sensitive.
Value Description
This bit defines whether the host interrupt is edge or
level-sensitive.
0 NHOSTINT is level-sensitive.
1 NHOSTINT is edge-sensitive.
This bit defines whether the nonmaskable interrupt is
edge or level-sensitive. The NMI channel corresponds to
the DSP NMI interrupt.
0 NMI is level-sensitive.
1 NMI is edge-sensitive.
This bit defines whether channel CHx is edge or
level-sensitive, where CHx corresponds to interrupt
channels nXIRQ[21:16]. Channels nXIRQ[21:16]
correspond to the DSP level 1 interrupts IRQ23:18,
respectively.
0 CHx is level-sensitive.
1 CHx is edge-sensitive.
DSP Interrupt Interface
Type
R/W
Type
R/W
R/W
R/W
DSP Private Peripherals
Reset
Value
0
Reset
Value
0
0
0
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