Level 2 Interrupts - Texas Instruments OMAP5910 Technical Reference Manual

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Table of Contents

Table 8–21. Level 1 Interrupt Mapping (Continued)

Level 1 Interrupt

DMA_channel_0

DMA_channel_2

DMA_channel_3

Level 2 Interrupts

The level 2 interrupt controller provides up to 16 prioritized and maskable inter-

rupts to the DSP core.

The level 2 interrupt controller resides on the 16-bit TI peripheral bus. This

module is clocked by the DSP_INTH_CK clock, which is fixed at half the

CK_GEN2 frequency (see Chapter 15 for details). Configuration registers

configure incoming interrupts as level-sensitive or edge-sensitive interrupts.

One interrupt-level register (ILR) is associated with each incoming interrupt.

It assigns a priority to the corresponding interrupt,determines whether it is to

be level- or edge-sensitive, and determines to which DSP interrupt (fast inter-

rupt request (FIQ) or low priority interrupt request (IRQ)) the incoming interrupt

goes. If several interrupts have the same priority level assigned, they are

serviced in a predefined order.

All level 2 interrupts are routed to FIQ. IRQ output is unconnected.

The interrupt controller also provides a 16-bit software interrupt register. This

16-bit register corresponds to the same 16-bit external interrupt lines. By writ-

ing a 1 to the targeted bit, an interrupt is generated if the corresponding ILR

is set to edge sensitive; otherwise, no interrupt is generated. External interrupt

request and internal software request are ORed together first before being

sent to the interrupt controller to be serviced. The software interrupt register

is always read back with a zero. This allows simulation of external interrupts

to test the corresponding interrupt driver by using the software interrupt

mechanism at any time.

The FIQ outputs from the interrupt controller are reset by writing a 1 to the

corresponding bit of the control register.

DSP Private Peripherals

Interrupt Handlers

IFR_bit/IMT_bit (26:0)