Receive Interrupt Timing Diagram; Transmit Interrupt Timing Diagram - Texas Instruments OMAP5910 Technical Reference Manual

Figure 9–10. Receive Interrupt Timing Diagram
CLK
Channel N-1
T7 T6 T5
RXD
IT_RX
t (syn) < 2 x DSPXOR_CK (12 MHz)
INTERRUPT_REG(3:0) = N–1
Transmit Interrupt
Figure 9–11.Transmit Interrupt Timing Diagram
CLK
Channel N-1
T7 T6 T5
TXD
IT_TX
t (syn) < 2 x DSPXOR_CK (MHz)
INTERRUPT_REG(7:4) = N
T4 T3 T2 T1 T0 T7
t (syn)
The transmit interrupt is generated every frame after the start of the transmis-
sion of a data word.
-
In single-channel mode, the interrupt is generated one clock period after
the beginning of the transmission of the word.
-
In multichannel mode, the interrupt is generated one clock period after the
transmission of the word of the channel whose number is defined by the
NB_CHAN_IT_RX parameter of INTERRUPTS_REG register.
T4 T3 T2 T1 T0 T7
t (syn)
T6 T5 T4 T3 T2 T1
Channel N
DSP_WRITE(1) => STATUS_REG(2)
T6 T5 T4 T3 T2 T1
Channel N
DSP_WRITE(1) => STATUS_REG(4)
Multichannel Serial Interfaces
Channel N+1
T0 T7 T6 T5 T4 T3
t (syn)
Channel N+1
T0 T7 T6 T5 T4 T3
t (syn)
DSP Public Peripherals
T2 T1 T0
T2 T1 T0
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