Sequence For Checking Faults - Texas Instruments OMAP5910 Technical Reference Manual

MPU Memory Management Unit
Figure 2–20. Sequence for Checking Faults
Section
transistor
fault
Section
No access (D0)
domain
Reserved (10)
fault
Section
permission
fault
2.7.11.1 Alignment Fault
2-44
Check address alignment
Get level 1 descriptor
Invalid
Section
Check domain status
Section
Client (0.1)
Check access
Violation
permissions
If an alignment fault is enabled (bit 1 in CP15 control register 1), the MMU gen-
erates an alignment fault upon 16-bit and 32-bit data accesses that are
improperly aligned (not on an address multiple of 2 and 4, respectively). The
TI925T checks the alignment even if the MMU is disabled.
Instruction fetches do not generate alignment faults; they always access
memory on 32-bit word boundaries.
Virtual address
Page
Get page
table entry
Page
Client (0.1)
Manager (0.1)
Check access
permissions
Physical address
Alignment
Misaligned
fault
Page
Invalid translation
fault
Page
No access (D0)
domain
Reserved (10)
fault
Subpage
permission
Violation
fault