Watchdog Timer Level 1 Interrupt - Texas Instruments OMAP5910 Technical Reference Manual

Watchdog Timer
6.3 Watchdog Timer
6.3.1 Introduction
Figure 6–4. Watchdog Timer
Watchdog timer
MPUWD_CK
0.86 MHz (12 MHz/14)
Table 6–8. Watchdog Timer Level 1 Interrupt
6-8
The watchdog timer (see Figure 6–4) can be configured as either a watchdog
timer or a general-purpose timer.
The watchdog timer is power-up enabled and defaults to watchdog timer for
the TI925T RISC processor. A watchdog timer requires that the user program
or OS periodically write to the count register before the counter underflows. If
the counter underflows, the watchdog timer generates a reset to the TI925T
RISC processor and to the TMS320C55x DSP. The watchdog timer detects
user programs stuck in an infinite loop, loss of program control, or a runaway
condition. When used as a general-purpose timer, the watchdog timer is a
16-bit timer configurable either in autoreload or one-shot mode with on-the-fly
read capability. The timer generates an interrupt to the TI925T RISC processor
when the count passes through zero (see Figure 6–5).
CLK
Divide clock down by
2 (PTV+1)
Timer
WD
LOAD_TIMER
Load when timer starts
CLK / 2 (PTV+1)
READ_TIMER
Watchdog module: RESET
Timer mode: IRQ_27
Corresponding Level 1 Interrupt
IRQ_27
If autoreload, then
load when timer
underflows
Reset or IRQ when
timer underflows