Pwl Block Diagram; Pseudonoise Pulse-Width Light Modulator - Texas Instruments OMAP5910 Technical Reference Manual

Pseudonoise Pulse-Width Light Modulator

7.6 Pseudonoise Pulse-Width Light Modulator
7.6.1 PWL Functional Description
Figure 7–21. PWL Block Diagram
RESET
CLK32
TIPB
7-50
This pulse-width light (PWL) module provides control of LCD backlighting and
keypad by employing a 4096-bit random sequence generator. This voltage-
level control technique decreases the spectral power at the modulator
harmonic frequencies. The module uses a 32-kHz clock from ULPD.
The PWL module is composed of a pseudorandom 8-bit data generator and
a programmable threshold comparator (see Figure 7–21).
The pseudorandom 8-bit data generator is built using an LFSR. It generates
a white normal-law random value between 1 and 255. The LFSR polynomial
generator is P(x) = x[7] + x[3] + x[2] + x[1].
The comparator generates:
-
0 if the random value is greater or equal than the programmable threshold
-
1 if the random value is less than the programmable threshold
Assuming the random sequence is normal, it generates a sequence whose
mean value is proportional to the comparator threshold.
RESET
8-bit PRBS generator
8
RESET
8
A
A<B
Comparator
A=B
B
8
PWL_LEVEL
register
RESET
PWL_OUT
Output
register
and test