Dsp External Memory Interface - Texas Instruments OMAP5910 Reference Manual

DSP External Memory Interface

5 DSP External Memory Interface
5.1 Overview
5.2 Peripheral Architecture
5.2.1 Clock Control
5.2.2 Memory Map
5.2.3 DSP External Memory Accesses
58 DSP Subsystem
The external memory interface (EMIF) gives the DSP core and the DSP DMA
controller access to the shared system memory managed by the traffic
controller. The EMIF interfaces directly to a 32-bit-wide system bus. This bus
can operate at the DSP subsystem clock rate with sustained throughput during
burst accesses.
Note:
Internally, 8-bit data read requests from DSP external memory are converted
to 16-bit data read requests by the EMIF. The appropriate byte is fetched
from this read request and placed in internal memory.
The relationship of the DSP EMIF to other DSP subsystem modules can be
seen from the system block diagrams in section 1.4.
The EMIF is clocked by the DSP subsystem clock DSP_CK (see section 12.2
for more details).
The EMIF controls accesses to DSP subsystem external memory. Section 3.4
details the memory map of the DSP subsystem.
Four major steps are taken when the DSP subsystem accesses DSP external
memory.
1) The DSP core or the DSP DMA requests an access to DSP external
memory.
2) The DSP EMIF receives that request and forwards it to the DSP MMU.
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