Dma Channel Element Index Register (Dma_Cei) - Texas Instruments OMAP5910 Technical Reference Manual

Table 5–23. DMA Channel Element Index Register (DMA_CEI)
Bit Name
15–0 Element index
Table 5–24. DMA Channel Progress Counter Register (DMA_CPC)
Bit Name
15–0 Last element/
frame address
16 LSB
Description
Contains the element index, expressed in bytes, used to
compute the addresses when single-index addressing
mode is used.
Description
This register can be used to monitor the progress of a
DMA transfer:
-
If the channel transfer is synchronized on elements
(DMA_CCR SYNC ≠ 0 and DMA_CCR FS = 0), the
register is updated with the address 16 LSB each time
the destination port issues the last request for an
element.
-
If the channel transfer is synchronized on frames
(DMA_CCR SYNC ≠ 0 and DMA_CCR FS = 1) or not
synchronized (DMA_CCR SYNC = 0), the register is
updated with 16 LSB of the address each time the
destination port issues the last request for a frame.
The DMA LCD control register contains seven bits that control the LCD chan-
nel operation. There are two cases of interruption: end frame buffer or abort
on the bus (bus error). Bit IE (interrupt enable) enables the generation of the
interruption.
If the COND bit and the corresponding IE bit are set, an interrupt signal is sent
from the DMA channel to the MPU. The MPU reads this register to find the
cause of the interruption.
-
COND = 0: Condition not detected
-
COND = 1: Condition detected
The COND bit is updated during a transfer, and the host processor must reset
this bit after reading.
Type
RW
Type
R
System DMA Controller
Registers
Reset
Value
Undefined
Reset
Value
Undefined
5-53