Mpu Core - Texas Instruments OMAP5910 Technical Reference Manual

MPU Core

2.2 MPU Core
2-4
The MPU core is a TI925T reduced instruction set computer (RISC) processor.
The TI925T is a 32-bit processor core that performs 32-bit or 16-bit instructions
and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all
parts of the processor and memory system can operate continuously.
The MPU core incorporates:
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A coprocessor 15 (CP15) and protection module
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Data and program memory management units (MMUs) with table look-
aside buffers.
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A separate 16K-byte instruction cache and 8K-byte data cache. Both are
two-way associative with virtual index virtual tag (VIVT).
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A 17-word write buffer (WB)
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A local bus interface
The OMAP5910 device uses the TI925T core in little endian mode only.
To reduce effective memory access time, the TI925T has an instruction cache,
a data cache, and a write buffer. In general, these are transparent to program
execution.