Cache Line Flush Registers (Flr0, Flr1); I-Cache Line Flush Register 0 (Flr0) Field Descriptions; I-Cache Line Flush Register 1 (Flr1) Field Descriptions; I-Cache N-Way Control Register (Nwcr) - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
Figure 13. I-Cache Line Flush Registers (FLR0, FLR1)
FLR0
15
FLR1
15
Reserved
Note: R = Read, W = Write; −n = Value after reset;, −x = Value after reset is not defined
Table 7.

I-Cache Line Flush Register 0 (FLR0) Field Descriptions

Bits Field
15−0 LINE_ADDRS_LOWER
Table 8.

I-Cache Line Flush Register 1 (FLR1) Field Descriptions

Bits Field
15−8 Reserved
7−0 LINE_ADDRS_UPPER
4.6.4

I-Cache N-Way Control Register (NWCR)

52 DSP Subsystem
LINE_ADDRS_LOWER
8
R-0
Value Description
0000h− Lower address bits of the line to be flushed.
FFFFh
Value Description
These bits are not used.
00h− Upper address bits of the line to be flushed.
FFh
The N-way control register (NWCR) controls certain features of the N-way
cache. You must configure this register before enabling the I-Cache through
CAEN.
The size of each way in the N-way cache must always be set to 8KB for all
devices.
The local flush and enable capabilities of the N-way cache are not supported
on OMAP5912 and OMAP5910. Always use the following configuration for the
N-way Control Register:
FLUSH = 1; the N-way cache is always flushed when CACLR is set.
-
ENABLE = 1; the N-way cache is always enabled when CACLR is set.
-
Any other setting for these bits is not supported.
RW-0
7
LINE_ADDRS_UPPER
0
0
RW-0
SPRU890A