Emif Slow Interface Configuration Register (Emifs_Config_Reg) - Texas Instruments OMAP5910 Technical Reference Manual

Traffic Controller Memory Interface Registers
Table 4–12. EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG)
Bit Field
31–5 Reserved
4 FR
3 PDE
2 PWD_EN
1 BM
0 WP
4-44
Value Description
Read is undefined. Writes must be zero.
Ready signal. This bit is a copy of the FLASH.RDY
input pin as sampled by TC clock.
0 FLASH.RDY pin is low.
1 FLASH.RDY pin is high.
Global power-down enable. This bit is used by EMIFS,
EMIFF, and IMIF as an enable for dynamic power down,
clock auto-gating. Note, however, that PDE must be set
in conjunction with individual power down bits for IMIF
and SDRAM before clocks will be cut.
0 Power down not enabled
1 Power down enabled
IMIF power-down enable. Controls IMIF internal clock
enable:
0 IMIF power down not enabled
1 IMIF power down enabled
Also note that PWD_EN is one of the prerequisites to
meet TC idle. PWD_EN must be set before the memory
interface can acknowledge a TC idle request.
MPU boot mode. This bit is sampled at reset from the
MPU_BOOT device pin. BM enables CS0 and CS3
address decode swapping.
0 CS0 [0000:0000 – 01FF:FFFF] CS3 [0C00:0000 –
0DFF:FFFF]
1 CS0 [0C00:0000 – 0DFF:FFFF] CS3 [0000:0000 –
01FF:FFFF]
Since BM is read/write, care must be exercised not to
write the bit since there is potential to inadvertently
modify EMIFS memory mapping.
Write protect bit. Enables write protection for all flash
devices.
0 FLASH.WP output pin is set low.
1 FLASH.WP output pin is set high.
Reset
Access
Value
R All 0
R x
R/W 0
R/W 0
R/W x
R/W 0