Control And Status Register (Csr) - Texas Instruments OMAP5910 Technical Reference Manual

MicroWire Interface
Table 7–29. Control and Status Register (CSR)
Bit Name
15 RDRB
14 CSRB
13 START
12 CS_CMD
7-32
Value Function
RDRB bit at 1 indicates that the receive (RDR)
is full. When the controller reads the content of
the RDR, this bit is cleared.
This bit is read only.
CSRB bit at 0 indicates that the control and
status (CSR) is ready to receive new data.
After starting a µWire transfer with the CSR,
this bit is set to 1. When the corresponding
action has been done, CSRB is reset. This bit
is controlled by a µWire internal state machine
running on the F_INT internal clock (12
MHz/N). If the CSR is read just after being
written and the MPU is running at high
frequency (60 MHz or 120 MHz, for instance)
compared to the internal clock, the CSRB
status bit may still be low for the first read
access. The CSRB latency is 0 if the transfer
was initiated by modifying the CS_CMD bit, but
it can be 0 – 3 cycles if initiated by the START
bit. Suggested workarounds are a) to have a
few NOPs between initiating a µWire transfer
and checking CSRB status or b) to check that
CSRB first has a high value on an initial read
before it goes low on a subsequent read.
This bit is read only.
1 Start a write and/or a read process.
This bit is automatically reset by internal logic
when a write or a read process is activated.
Send NB_BITS_WR bits (contained in TDR) to
the serial output DO. If NB_BITS_WR is equal
to zero, then the write process is not started.
Receive NB_BITS_RD bits from the serial input
DI and store them in RDR.
1 Set the chip-select of the selected device to its
active level.
Reset
Value
0
0
0
0