Setup Register 5 (Sr5) (Read/Write) - Texas Instruments OMAP5910 Technical Reference Manual

Table 7–34. Setup Register 5 (SR5) (Read/Write)
Bit Name
3 CS_TOGGLE_TX_EN
2 AUTO_TX_EN
1 IT_EN
0 DMA_TX_EN
Note: Content of this register must not be changed when a read or write process is running.
Value Function
CS_TOGGLE_TX_EN is possible only in
autotransmit mode.
When in autotransmit mode with
CS_TOGGLE_TX_EN inactive, the CS does
not go to its active level automatically. Control
the CS with the CS CMD bit of the control and
status register (CSR) in the software.
0 CS_toggle transmit mode is disabled if 0.
1 CS_toggle transmit mode is enabled if 1.
In autotransmit mode, the CS_CMD and
START bits of the control and status register
(CSR) are not used. A hardware state machine
detects a TXD write and automatically sets the
programmed CS to its active value, then starts
the transmission.
The CS-CMD and the START bits in the control
and status register (CSR) are not updated
during autotransmit.
0 Autotransmit mode is disabled if 0.
1 Autotransmit mode is enabled if 1.
In IT mode, an interrupt is generated each time
a word has been transferred or a received. This
interrupt is a negative edge-triggered interrupt.
A status register (IST) allows the CPU to know
which interrupt (receive or/and transmit)
occurred.
0 IT mode is disabled if 0.
1 IT mode is enabled if 1.
0 DMA transmit mode is disabled if 0.
1 DMA transmit mode is enabled if 1.
MicroWire Interface
MPU Public Peripherals
Reset
Value
0
0
0
0
7-37