Dma Channel Interrupt Control Register (Dma_Cicr) - Texas Instruments OMAP5910 Technical Reference Manual

Registers
Table 5–14. DMA Channel Interrupt Control Register (DMA_CICR)
Bit Name
15–7 RESERVED
6 RESERVED
5 BLOCK_IE
4 LAST_IE
3 FRAME_IE
2 HALF_IE
1 DROP_IE
5-48
Value Description
End block interrupt enable
0 The channel does not interrupt the processor when the
transfer of the block completes.
1 The channel sends an interrupt to the processor when
the transfer of the block completes.
Last frame interrupt enable
0 The channel does not interrupt the processor when the
transfer of the last frame starts.
1 The channel sends an interrupt to the processor when
the transfer of the last frame starts.
Frame interrupt enable
0 The channel does not interrupt the processor when the
transfer of the current frame completes.
1 The channel sends an interrupt to the processor when
the transfer of the current frame completes.
Half frame interrupt enable
0 The channel does not interrupt the processor when the
transfer of the first half of the current frame completes.
1 The channel sends an interrupt to the processor when
the transfer of the first half of the current frame
completes.
Synchronization event drop interrupt enable
0 The channel does not interrupt the processor when a
synchronization event drop occurs.
1 The channel sends an interrupt to the processor if the
channel transfer is synchronized on DMA requests and
on successive DMA request drops. This occurs when
a new DMA request is made while the service of the
previous one is not finished yet.
Reset
Type Value
R 0
RW 0
RW 0
RW 0
RW 0
RW 1