Level-Sensitive Interrupts - Texas Instruments OMAP5910 Technical Reference Manual

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DSP Interrupt Interface

Level-Sensitive Interrupts

Internal Registers

The level-sensitive interrupt process is, in many ways, identical to the edge-

triggered interrupt process. This process also uses a chain of four positive-

edge triggered timing flip-flops, but this chain is driven by the inverted repre-

sentation of the incoming interrupt nXIRQ(N). A negative transition (falling

edge) on the incoming nXIRQ(N) line activates the output interrupt nIRQ(N)

and must be held low for one DSP_INTH_CK cycle (which is equivalent to two

DSP_CLK cycles) to be recognized by the DSP. Even when nXIRQ(N) remains

at 0 for a time period exceeding three to four DSP_INTH_CK periods (depend-

ing on when the asynchronous falling edge of nXIRQ(N) occurs with respect

to the rising edge of DSP_INTH_CK), the interrupt nIRQ(N) remains activated

until the nXIRQ(N) is deactivated. However, the DSP recognizes this as only

one interrupt, because there was only one falling edge of nIRQ(N).

DSP word start address: 0x003800

Bit width: 16 bits

DSP word address of a register = start word address + offset address

The DSP_INT_IF has two control registers (one 16-bit and one 7-bit) and two

clear command registers (one 16-bit and one 7-bit). The control registers are

used exclusively for assigning edge-triggered/level-sensitive status to each of

the 23 interrupt channels. The clear command registers are not actual physical

registers, but rather a block of decoding logic that issues clear commands to

the level-sensitive logic in each interrupt channel upon detecting a TIPB write

transaction to an address that falls within the required address range.

The bit-alignment of interrupt channel assignments within the control register,

the definition of the assignments, the default values at power turn-on, the

address used to write to the control register, and the address used to read the

content of the register are all presented in Table 8–31 through Table 8–34.