I-Cache Global Control Register (Gcr) Bits Field Descriptions - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
Table 6.

I-Cache Global Control Register (GCR) Bits Field Descriptions

Bits Field
15 CUT_CLOCK
14 AUTO_GATING
13 Reserved
12 FLUSH_LINE
11 GLOBAL_FLUSH
10 HLFRAMSET_
PRESENCE
9 WAY_PRESENCE
50 DSP Subsystem
Value Description
This bit determines whether the I-Cache module clock is disabled or
enabled when the I-Cache is disabled.
0 Disabled.
1 Enabled.
Enables automatic clock gating
0 Disabled.
1 Enabled.
This reserved bit must be kept as 0.
Setting this bit flushes the lines specified by the flush line registers.
0 No flush.
1 Flush the specified line. Once the line flush occurs, the flush line bit is
automatically cleared by the I-Cache.
Setting the CACLR bit of the DSP core ST3_55 register begins a flush
process within the I-Cache. The N-way cache and the two RAM set
blocks contain a flush bit in their control registers, NWCR and RCR1/2,
respectively. The GLOBAL_FLUSH bit determines whether the local
flush bits are taken into consideration when CACLR is set.
0 The N-way cache and the RAM set blocks are flushed when CACLR
is set only if their local flush bits are set.
1 The entire cache is flushed when CACLR is set; the local flush bits are
ignored.
This bit is used to enable the RAM set blocks. The number of RAM set
blocks that are enabled is specified through the HLFRAMSET_NUMR
bits.
0 RAM set blocks are disabled.
1 RAM sets blocks are enabled.
This bit is used to enable the N-way cache block. The number of ways
is specified in through the WAY_NUMR bits.
0 N-way cache block is disabled.
1 N-way cache block is enabled.
SPRU890A