Mmu Pre-Fetch Register (Prefetch_Reg) - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
Table 21. Summary of DSP MMU Registers (Continued)
Name
GFLUSH_REG
FLUSH_ENTRY_REG
READ_CAM_H_REG
READ_CAM_L_REG
READ_RAM_H_REG
READ_RAM_L_REG
DSPMMU_IDLE_CTRL
†
MPU byte addresses apply to both OMAP5910 and OMAP5912.
‡
This register is accessible by the DSP core at I/O address 0x4400.
6.5.2

MMU Pre-Fetch Register (PREFETCH_REG)

102 DSP Subsystem
Description
Global flush register. Use this bit to flush all
non-preserved entries from the TLB.
Individual flush register. Use this register to flush a
single entry from the TLB.
Read CAM registers. When reading from the TLB, the
CAM value is retrieved from these registers.
Read RAM registers. When reading from the TLB, the
RAM value is retrieved from these registers.
MMU Idle Control register. Use this register to control
the power-down capabilities of the DSP MMU.
The table walking logic automatically fetches an entry for the TLB when a TLB
miss is generated. The DSP core can force the table walking logic to pre-fetch
an entry for the TLB by writing a virtual address tag to the PREFETCH_REG.
Note that the virtual address tag corresponds to the 14 most-significant bits of
a virtual address.
The status of the pre-fetch operation is shown in the PREFETCH_ON bit of the
WALKING_ST_REG.
This register is visible from both the DSP side and the MPU side; however, on
the DSP side this register is write-only; and on the MPU side this register is
read-only.
MPU Byte See
Address † Section
0xFFFE D23C 6.5.13
0xFFFE D240 6.5.14
0xFFFE D244 6.5.15
0xFFFE D248
0xFFFE D24C 6.5.16
0xFFFE D250
0xFFFE D254 6.5.17
SPRU890A