Transmit Control Register 2 Configuration (Dsp_Write(0X80A1) => Xcr2) - Texas Instruments OMAP5910 Technical Reference Manual

McBSP1
Table 9–9. Transmit Control Register 2 Configuration (DSP_Write(0x80a1) => XCR2)
Bit Config Value
15 1b
14–8 000 0000b
7–5 101b
4:3 00b
2 0b
1:0 01b
9.3.4.5 Sample Rate Generator Configuration (SRGR[1,2])
9.3.4.6 DMA Configuration
9.3.4.7 Interrupt Flag Configuration and Clear (ILR, MIR)
9.3.4.8 Take out of Reset for Transmit and Receive Starting (SPCR[1,2])
9-10
DSP_Write(0x80a1) => XCR2; set up XCR2 as shown in Table 9–9.
Description
Set dual-phase frame
Don't care for single-phase frame
Set receive word length as 32 bits per frame
Set no companding data and transfer start with MSB first
Set FSX not ignore after the first resets the transfer
Set data delay as 1 bit
It is not necessary to configure the sample rate generator, because external
clocks and frames are provided appropriately for CLKX and FSX.
It is necessary to configure the REVT and XEVT bit for the DMA receive and
transmit synchronized invent.
1) DSP_Write => ILR; set ILR appropriately for the interrupt handling priority.
2) DSP_Write MIR and (0x0000 0030) => MIR; disabled SPI TX and RX
interrupt
Note:
Enable the appropriate DMA channel interrupts.
1) DSP_write SPCR1 or (0x0001) => SPCR1; enabled receive port
2) DSP_write SPCR2 or (0x0001) => SPCR2; enabled transmit port