D-Cache Clean/Flush Single Entry Operand Format - Texas Instruments OMAP5910 Technical Reference Manual

Coprocessor 15
Table 2–10. Cache Operations (Continued)
Function
Clean D-cache entry
Clean and flush D-cache entry
(4)
Clean D-cache
Prefetch I-line
Wait-for-interrupt
Drain write buffer
Notes: 1) Flush I- and D-cache operations invalidate all entries in the I-cache and D-cache respectively. The flush D-cache
also discards any dirty lines present in the D-cache.
2) The flush D-cache and D-cache entry operations do not clean the D-cache entries before they are invalidated.
A clean and flush D-cache requires two cache operations; there is a specific operation for cleaning and flushing
a D-cache entry at once. First clean then flush the entire cache; this requires two CP15 operations (bear in mind
the VIVT clean algorithm). You can clean and flush individual entries in one CP15 operation.
3) Figure 2–6 shows the format of the Rd value for all D-cache operations on a single entry.
4) TI925T supports high performance full cache clean operation with the VIVT algorithm.
Figure 2–6. D-Cache Clean/Flush Single Entry Operand Format
31 X
A
2-20
Opcode_2 CRm
0b010 0b1010
0b010 0b1110
0b000 0b1010
0b001 0B1101
0b100 0b0000
0b100 0b1010
SBZ
There are two valid fields. The A-field depends on the level of associativity of
the cache. The L-field depends on the number of lines per set.
The CIR register (cache information) provides all the information to calculate
x, y, and z following the equations below:
x = 32 – CIR[17 – 15] – CIR[14]
y = 8 + CIR[20 – 18] – CIR[17-15]
z = CIR[13 – 12] + 3
In addition, one bit (D-cache clean entry mode) of TI925T configuration regis-
ter allows cleaning of one entry in both sets at a time. D[31] becomes don't care
when the D-cache clean entry mode is zero (see CP15 register 15 description).
In this mode, the software clean operation just cleans one block of virtual
memory with an increment corresponding to the line size.
Rd Instruction
(3)
Set/Index MCR p15, 0, Rd, c7, c10, 2
(3)
Set/Index MCR p15, 0, Rd, c7, c14, 2
SBZ MCR p15, 0, Rd, c7, c10, 0
VA MCR p15, 0, Rd, c7, c13, 1
SBZ MCR p15, 0, Rd, c7, c0, 4
SBZ MCR Rd, c7, c10, 4
Y
L
Z 0
SBZ