Sdram Internal Organization - Texas Instruments OMAP5910 Technical Reference Manual

Table 4–16. EMIF Fast Interface SDRAM Configuration Register 1
(EMIFF_SDRAM_CONFIG) (Continued)
Bit Field
1 SD_RET
0 SLRF
Table 4–17. SDRAM Internal Organization
Value Description
SDRAM retiming:
0 Data is single buffered with the return clock from
SDRAM.
1 Data from SDRAM is double buffered. Data is first
clocked on return clock from SDRAM, then with
the OMAP5910 internal SDRAM clock.
When set, places the SDRAM in self-refresh
mode. Mode is automatically exited upon the
generation of any SDRAM access.
This register is used to configure the SDRAM, interface timing, autorefresh
setup, and powerdown modes of the EMIFF interface. Table 4–17 describes
the internal organization. Table 4–18 describes the frequency range.
Register Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
† Unavailable bank number (not supported). Do not use this setting.
Note: Reset value = 0x2h.
Traffic Controller Memory Interface Registers
Memory Size
Size Of Data Bus
(M Bits)
16
64
128
Memory Interface Traffic Controller
Reset
Access
Value
R/W
R/W
Number Of
Banks
8 2
†
8 4
16 2
†
16 4
8 2
8 4
16 2
16 4
†
8 2
8 4
0
0
4-49