Controller Access Mode And Data Access Width - Texas Instruments OMAP5910 Technical Reference Manual

Introduction
Table 4–1. Controller Access Mode and Data Access Width
Controllers
MPU
C55x DSP
System DMA controller
Local bus
4-4
Single Access Mode
Data Access Width
(Bits)
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
The memories accessed by the TC are separated into two groups:
-
External memory is memory that is not part of the OMAP5910 device. It
can be SDRAM, flash, ROM, RAM, etc. External memory is accessed
using the external memory interface (EMIF). The TC has two separate
memory interfaces to access the external memories.
J
External memory interface fast (EMIFF): A fast synchronous interface
for SDRAM
J
External memory interface slow (EMIFS): An asynchronous/synchro-
nous interface to handle flash, ROM, RAM, etc.
-
Internal memory is memory that is part of the OMAP5910 device and
consists of 192K bytes of SRAM. The TC accesses the internal memory
using an internal memory interface (IMIF) that is part of the TC.
Four hosts access the system resources using the TC.
-
MPU: The MPU is connected to the TC via the MPU bus. The MPU can
access memories that are connected to the IMIF, EMIFF, and EMIFS.
-
C55x DSP: The C55x DSP is connected to the TC via the DSP MMU bus.
The C55x DSP can access memories connected to IMIF, EMIFF, and
EMIFS.
-
System DMA: The system DMA is connected to the TC using four sepa-
rate 32-bit buses, providing the system DMA controller with concurrent
access to memories connected to the IMIF, EMIFF, and EMIFS.
-
Internal local bus interface: An internal local bus interface is connected to
the TC to allow access to memories connected to IMIF, EMIFF, and
EMIFS. In OMAP5910, the USB host controller interfaces (and is master)
to the local bus.
Burst Access Mode
Data Access Width
(Bits) Remarks
32 Single and burst access
32 Single and burst access
16, 32 Single and burst access; the
16-bit burst access is reserved for
the LCD controller channel
32 Single and burst access