Prefetch Register (Prefetch_Reg)) - Offset Address (Hex); Prefetch Status Register (Walking_St_Reg) - Offset Address (Hex) - Texas Instruments OMAP5910 Technical Reference Manual

DSP Memory Management Unit
Table 2–26. DSP Memory Management Unit Registers (Continued)
Name
RAM_L_REG
GFLUSH_REG
FLUSH_ENTRY_REG
READ_CAM_H_REG
READ_CAM_L_REG
READ_RAM_H_REG
READ_RAM_L_REG
Table 2–27. Prefetch Register (PREFETCH_REG)) – Offset Address (hex): 00
Bit Function
15 Reserved
14 The data to prefetch is data when 1, program when 0.
13–0 MSB of virtual address tag of the TLB entry to be prefetched
Table 2–28. Prefetch Status Register (WALKING_ST_REG) – Offset Address (hex): 04
Bit Function
15–2 Reserved
1 When 1, table walking is running.
0 Writing in the prefetch data register sets this bit; the acknowl-
edge of the prefetch resets the bit.
2-48
Description
RAM entry register LSB
Global flush register
Individual flush register
Read CAM MSB
Read CAM LSB
Read RAM MSB
Read RAM LSB
R/W Size Address
R/W 16 bits FFFE:D238
R/W 16 bits FFFE:D23C
R/W 16 bits FFFE:D240
R/W 16 bits FFFE:D244
R/W 16 bits FFFE:D248
R/W 16 bits FFFE:D24C
R/W 16 bits FFFE:D250
Size Access
1
1
14
Size Access
14
1
1
Reset Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Value at
Hardware
Reset
R/W 0
R/W 0
Value at
Hardware
Reset
R 0
R 0