Pwl Registers - Texas Instruments OMAP5910 Technical Reference Manual

7.6.2

PWL Registers

Table 7–41. PWL Registers
Name Description
PWL_LEVEL PWL-level
PWL_CTRL PWL control
Table 7–42. PWL Level Register (PWL_LEVEL)
Bit Name
7–0 PWL_LEVEL
Table 7–43. PWL Control Register (PWL_CTRL)
Bit Name
7–1 –
0 CLK_ENABLE
The PWL is connected to the host with a TIPB. The PWL control is done with
two 8-bit registers. All TIPB accesses are done asynchronously with the
32-kHz clock, meaning there is no TIPB wait-state insertion.
Table 7–41 lists the PWL registers. Table 7–42 and Table 7–43 describe the
individual registers.
Start address (hex): FFFB:5800
Offset address (hex): 0x00
Function
Defines the mean value of the PWL output signal. 0
leads to a continuous 0 output. 255 to an almost
continuous 1 output: 255/256 cycles in high level.
Offset address (hex): 0x04
Function
Reserved
Internal clock is enabled when 1.
Pseudonoise Pulse-Width Light Modulator
R/W Size Address
R/W 8 bits FFFB:5800
R/W 8 bits FFFB:5800
MPU Public Peripherals
Offset
0x00
0x04
Reset
Value
0
Reset
Value
0
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